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Note:
PIC16C72A PIC16F72 Migration
DEVICE MIGRATIONS
This document is intended to describe the differences that are present when migrating from one device to the next. Table 1 and Table 2 list the data memory organization differences and the additional Special Function Registers, Table 3 lists the differences in functionality, and Table 4 through Table 7 list the differences in the electrical and timing specifications.
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
Note:
The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the oscillator mode may be required.
TABLE 1:
No. 1 2 3 4 5 6 7 BANK 2 BANK 3
PIC16C72A PIC16F72 DATA MEMORY DIFFERENCES
SFR Differences from PIC16C72A BANK 2 is implemented BANK 3 is implemented Implemented Implemented Implemented Bit 6 (RP1) and Bit 7 (IRP) are implemented Bit 2 (TMR0IF) and Bit 5 (TMR0IE) Address register pair Data register pair Control register for memory access RP1 to access BANK 2 & 3, IRP used for indirect addressing T0IF and T0IE in PIC16C72A Comment
PMADRH:PMADRL PMDATH:PMDATL PMCON1 STATUS INTCON
2002 Microchip Technology Inc.
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DS39566A-page 1
TABLE 2:
Address Bank 2 100h(1) 101h 102h(1 103h(1) 104h(1) 105h 106h 107h 108h 109h 10Bh(1) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(1) 181h 182h(1) 183h(1) 184h(1) 185h 186h 187h 188h 189h 18Bh(1) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: 4: INDF OPTION PCL STATUS FSR -- TRISB -- -- -- INDF TMR0 PCL STATUS FSR -- PORTB -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(3)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu
Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- TMR0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR0IF INTF RBIF
--
xxxx xxxx
--
uuuu uuuu
-- -- --
---0 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
-- -- --
---0 0000 0000 000u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
10Ah(1,2) PCLATH INTCON PMDATL PMADRL PMDATH PMADRH
Data Register Low Byte Address Register Low Byte -- -- -- -- Data Register High Byte -- Address Register High Byte
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
1111 1111 0000 0000 1111 1111 0000 0000 000q quuu uuuu uuuu
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx
Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE --
(4)
--
1111 1111
--
1111 1111
-- -- --
-- -- --
---0 0000 0000 000u 1--- ---0
18Ah(1,2) PCLATH INTCON PMCON1 -- -- --
-- PEIE --
-- TMR0IE --
Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- TMR0IF -- INTF -- RBIF RD
---0 0000 0000 000x 1--- ---0
Unimplemented Reserved maintain clear Reserved maintain clear
--
0000 0000 0000 0000
--
0000 0000 0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. These registers can be addressed from any bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. This bit always reads as a `1'.
DS39566A-page 2
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FIGURE 1:
PIC16F72 BANK 2 & 3 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTB 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h PCLATH INTCON PMDATL(1) PMADRL(1) PMDATH(1) PMADRH(1) Bank 2 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh Bank 3 PCLATH INTCON PMCON1(1) TRISB Indirect addr.(*) OPTION PCL STATUS FSR File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh
Unimplemented data memory locations, read as `0'. * Not a physical register. Note 1: New registers implemented in 16F72.
TABLE 3:
No. 1 Module
PIC16C72A PIC16F72 FUNCTIONAL DIFFERENCES
Differences from PIC16C72A The FLASH Program Memory is readable during normal operation Issues may exist with regard to the application circuit. Issues may exist with regard to the user program. Issues may exist with regard to programming. H/W -- S/W Yes Prog --
Program Memory Read Legend:
H/W S/W Prog. -
2002 Microchip Technology Inc.
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DS39566A-page 3
READING PROGRAM MEMORY
The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP. There are five SFRs used to read the program and memory: * * * * * PMCON1 PMDATL PMDATH PMADRL PMADRH
When interfacing to the program memory block, the PMDATH:PMDATL registers form a two-byte word that holds 14-bit data for reads. The PMADRH:PMADRL registers form a two-byte word that holds the 13-bit address of the FLASH location being accessed. This device can have up to 2K words of program FLASH, with an address range from 0h to 07FFh. The unused upper bits in both the PMDATH and PMADRH registers are not implemented and read as zeroes.
PMADR
The address registers can address up to a maximum of 8K words of program FLASH. When selecting a program address value, the MSByte of the address is written to the PMADRH register and the LSByte is written to the PMADRL register. The upper MSbits of PMADRH must always be clear.
The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration tables.
PMCON1 Register
PMCON1 is the control register for memory access. The control bit, RD, initiates read operations. This bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the read operation.
REGISTER 1:
PMCON1: PROGRAM MEMORY CONTROL REGISTER (ADDRESS: 18Ch)
R-1 reserved bit 7 U-0 -- U-0 -- U-0 -- U-x -- U-0 -- U-0 -- R/S-0 RD bit 0
bit 7 bit 6-1 bit 0
Reserved: Read as `1' Unimplemented: Read as `0' RD: Read Control bit 1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a FLASH read Legend: S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' R = Readable bit `0' = Bit is cleared -n = Value at POR x = Bit is unknown
DS39566A-page 4
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REGISTER 2:
U-1 -- bit13 bit 13-7 bit 6 U-1 -- U-1 --
CONFIGURATION WORD (ADDRESS: 2007h)(1)
U-1 -- U-1 -- U-1 -- U-1 -- u-1 BOREN U-1 -- u-1 CP u-1 u-1 u-1 u-1 bit0 Unimplemented: Read as `1' BOREN: Brown-out Reset Enable bit(2) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `1' CP: FLASH Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: Enabling Brown-out RESET automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. PWRTEN WDTEN F0SC1 F0SC0
bit 5 bit 4
bit 3
bit 2
bit 1-0
Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' u = Unchanged from programmed state - n = Value when device is unprogrammed
2002 Microchip Technology Inc.
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DS39566A-page 5
REGISTER 3:
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) Each bank is 128 bytes 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1,2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. 2: For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39566A-page 6
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2002 Microchip Technology Inc.
TABLE 4:
PIC16C72A PIC16F72 ELECTRICAL CHARACTERISTICS DIFFERENCES
Characteristic PIC16C72A Data Sheet PIC16F72 Data Sheet -0.3 to 7.5 0 to 13.25 0 to 8.5 -0.3 to 6.5 0 to 13.5 0 to 12 Units V V V
Voltage on VDD with respect to VSS Voltage on MCLR with respect to VSS (Note 1) Voltage on RA4 with respect to VSS
Note 1: It is recommended to not tie the MCLR pin directly to VDD (see Figure 11-5 in the PIC16F72 Data Sheet for the recommended MCLR circuit).
TABLE 5:
Parm. No. D010 D013 Sym.
PIC16C72A PIC16F72 ELECTRICAL SPECIFICATION DIFFERENCES
PIC16C72A Data Sheet Characteristic Min Typ 2.7 Max 5.0 PIC16F72 Data Sheet Min -- Typ 0.9 Max 4.0 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 10 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT enabled, -40C to +85C BOR Enabled, VDD = 5.0V Units Conditions
IDD
Supply Current (Notes 1, 2)
--
-- D020 D021 D023* IBOR
*
10.0 10.5 1.5 TBD
20.0 42.0 19.0 200
-- -- -- --
5.2 5.0 0.1 25
15.0 42.0 19.0 200
mA
A A A
IPD
Power-down Current (Notes 2,3)
-- --
Brown-out Reset Current (Note 5)
--
Note 1:
2: 3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. Timer1 oscillator (when enabled) adds approximately 20 mA to the specification. This value is from characterization and is for design guidance only. This is not tested. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
2002 Microchip Technology Inc.
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DS39566A-page 7
TABLE 6:
Parm. No. Sym.
PIC16C72A PIC16F72 DC CHARACTERISTICS DIFFERENCES
PIC16C72A Data Sheet Characteristic Min Input High Voltage Open Drain High Voltage Program FLASH Memory Endurance VDD for Program FLASH Memory Read 0.7 VDD 0.7 VDD -- -- -- Typ -- -- -- -- -- Max VDD VDD 8.5 -- -- Min 1.6 0.7 VDD -- 100 2.0 Typ -- -- -- 1000 -- Max VDD VDD 12 -- 5.5 V V V OSC1 (in XT and LP mode) OSC1 (in HS mode) (Note 1) RA4 pin PIC16F72 Data Sheet Units Conditions
D042A VIH D150* VOD D130 D131 * EP VPR
E/W 25C at 5V V
Note
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. 1: For RC osc configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F72 be driven with external clock in RC mode.
TABLE 7:
Parm. No. A020 131 Sym. VREF TCNV
PIC16C72A PIC16F72 ADC MODULE DIFFERENCES
PIC16C72A Data Sheet Characteristic Min Reference Voltage Conversion Time (not including S/H time) (Note 1) 2.5 2.5 11 Typ -- -- -- Max VDD+0.3 VDD+0.3 11 Min 2.5 2.2 9 Typ -- -- -- Max VDD+0.3 VDD+0.3 9 V V TAD -40C to +85C 0C to +85C PIC16F72 Data Sheet Units Conditions
*
Note 1:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. ADRES register may be read on the following TCY cycle.
DS39566A-page 8
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2002 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
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DS39566A - page 9
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